Architecture of Vedic Multiplier

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For addition

Sum(i) = x(i) XOR y(i) XOR c(i-1) , 0 ≤ i ≤ N-1

Where i represent the current ith value and the range of i is between zero (0) to N-1.The result of this calculation is saved in ith value of sum(i).Each 1-bit adder in above Figure. 4 is described by above mentioned formulas.

For carry generation:

C(i) = x(i)y(i)+ x(i)c(i-1) + y(i)c(i-1) , 0 ≤ i ≤ N-1

Cout=c(N-1) and c(-1)= Cin

Where i represent the current ith value and the range of i is between zero (0) to N-1.The result of this calculation is saved in ith value of sum(i). Each 1-bit carry generated in above Figure.4. is described by above mentioned formulae.

4 x 4 Vedic Multiplier:

The 4x4 Multiplier is made by using 4, 2 2 multiplier sub blocks[4]. Here, the multiplicands are having the bit size of (n=4) whereas, the result is of 8 bit in size. The input is broken in to smaller groups of size of n/2 = 2, for both inputs, that is a and b. These newly formed groups of 2 bits are given as input to 2 2 mult iplier block and the result produced 4 bits, which are the output produced from 2 2 multiplier block are sent for addition to an addition tree.

[pic 3]

Figure 5: Hardware realization of 4×4 multiplier

With these 4×4 multiplier blocks we can design 128×128bit mult iplier by structural modeling as we have already developed the generic adder.

For the ease of reading the figure6 lets take

Y=00000000000000000000000000000000000000000000 00000000000000000000

[pic 4]

Figure 6. Shows the hardware realization diagram of an 128×128 multiplier.