Ee2021
Autor: Mikki • October 7, 2018 • 2,055 Words (9 Pages) • 464 Views
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From the plot, [pic 11]= 0.0502, Kn = 0.00252 A V-2 = 2.52 mA V-2;[pic 12]
[pic 13]= 0.0403 VTHN = 0.803 V.[pic 14]
(c) Any of the following ways can be used to increase Kn :
Method 1 : Increase COX by reducing the oxide thickness,
Method 2 : Increase COX by using a dielectric material with higher permittivity.
Method 3 : Increase the width W of the MOSFET,
Method 4 : Reduce the length L of the MOSFET.
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Q2. An n-channel MOSFET has the following parameters : threshold voltage VTH = 0.75 V, gate oxide thickness tox = 40 nm and channel length L = 1 μm. The following parameters may be used : mobility of the electrons in the inversion channel, μn = 525 cm2 V-1s-1; temperature, T = 300 K; relative permittivity of the gate oxide, εr,SiO2 = 3.9.
(a) Calculate the gate oxide capacitance per unit area of the MOSFET.
(b) Determine the channel width W such that when the MOSFET is biased in the saturation region, the drain current IDsat = 6 mA when the gate-source voltage, VGS = 5V.
(c) Fig. Q2 shows partially the schematic cross-sectional view of an n-channel MOSFET, and the applied biases.
[pic 15]
Fig. Q2
The MOSFET is biased such that VGS = 5 V. For each of the following cases, determine whether the MOSFET is operating in the linear region or the saturation region. Calculate the drain current ID and sketch the shape of the channel in Fig. Q2.
(i) VGD = 0 V;
(ii) VGD = 2 V.
VGD is the voltage at the gate with respect to the drain.
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2. (a) Oxide capacitance per unit area:
[pic 16]
(b) For the MOSFET to operate in saturation region with IDsat = 6 mA,
[pic 17]
[pic 18]
[pic 19]
(c) When VGS = 5 V, VDSsat = VGS – VTH = 5 - 0.75 = 4.25 V.
- When VGD = 0, VDS = VGS = 5 V > VDSsat.
The MOSFET is operating in the saturation region.
ID = IDsat = 6 mA.
[pic 20]
[pic 21]
[pic 22]
Note: Shape of channel shown should be triangular and the tip should terminate before the edge of the drain.
(ii) When VGD = 2 V, VDS = VGS – 2 = 3 V VDSsat.
The MOSFET is operating in linear region.
Since VGS = 5 V, VDS = 3 V,
[pic 23]
[pic 24]
Note: Shape of the channel should be trapezoidal and extends from source to drain.
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Q3. An n-channel MOSFET has the following device parameters: threshold voltage VTH = 0.8 V, channel carrier mobility µn = 575 cm2 V-1 s-1, channel width W = 15 µm and channel length L = 1 µm. The source and body are connected together and grounded. Channel length modulation is negligible. The permittivity of free space, ε0 = 8.854×10-14 F cm-1. The relative permittivity of silicon, εr,Si = 11.7 and the relative permittivity of SiO2, εr,SiO2 = 3.9.
(a) Design the gate oxide thickness of this n-channel MOSFET such that when it is operating in the saturation region with a gate-source voltage VGS = 6 V and a drain-source VDS = 6 V, the drain current ID = 8 mA.
(b) The drain current of this MOSFET ID = 6.5 mA for a drain-source voltage VDS = 2 V. Assume that the MOSFET is operating in the linear region, calculate the gate-source voltage VGS. Hence verify whether the assumption that the MOSFET is operating in the linear region is valid.
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3. (a) For the n-channel MOSFET operating in the saturation region,
[pic 25]
[pic 26]
[pic 27]
tox= 50 nm
(b)
[pic 28]
VGS = 7.293 V.
VDS, SAT =VGS - VTH = 7.293 - 0.8 = 6.493 V.
VDS = 2V VDS, SAT, so this n-channel MOSFET is operating in the linear region.
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Q4. Figure Q4 shows a single stage amplifier circuit which employs a p-MOSFET. The parameters of the p-MOSFET are: Kp = 0.5 mA V-2, VTH = -1 V. Assume that channel length modulation effect is negligible.
[pic 29]
ID = 0.6 mA
VS
VDD = 5 V
RS
vin
R2
45 kΩ
VG
R1
75 kΩ
C
Fig. Q4
(a) Determine VG, the voltage at the gate of the MOSFET.
(b) Express VS, the voltage at the source of the MOSFET, in
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